The present invention relates to a semiconductor chip on which an integrated circuit and the like for driving a display panel are formed. More particularly the present invention includes a semiconductor device package mounted with the semiconductor chip, a probe card for use in testing the semiconductor device package and a package testing method using the probe card.
Conventional methods for mounting an LCD (liquid crystal display) driver chip on an LCD device include the COG (chip on glass) mounting method for directly mounting the chip on a lower glass substrate of an LCD panel and the TCP (tape carrier package) mounting method. In the TCP mounting method, a tape-shaped TCP on which the LCD driver chip is mounted is used, and the LCD driver chip is mounted on the periphery of the LCD panel by bonding electrodes provided on the lower glass substrate of the LCD panel and a conductor pattern on the TCP via ACF (anisotropic conductive film) in a thermocompression bonding manner.
The above-mentioned TCP is constructed as shown in FIG. 10. In FIG. 10, a plurality of LCD drivers 2, 2, . . . are mounted at regular intervals in a line in a specified direction on a tape-shaped substrate 1. Each LCD driver 2 is constructed of an LCD driver chip 3, input leads 4, output leads 5, input testing terminals 6 and output testing terminals 7. Then, each LCD driver 2 is punched according to a TCP punching size indicated by the dashed lines 8 and formed into the final shape of the LCD driver 2.
Each LCD driver chip 3, to be arranged on the substrate 1, is placed in a position where the coordinate of the centers of sprocket holes 9 and 10 formed at regular intervals on both sides of the substrate 1 coincide with the coordinate of the center of the LCD driver chip 3 in the lengthwise direction (see the LCD driver chip 3 located in the rightmost position on FIG. 10). Therefore, LCD driver chips 3 are arranged at intervals of an integral multiple of the pitch of the sprocket holes 9, 10. For example, the pitch of the sprocket holes 9, 10 is standardized to 4.75 mm according to JIS in the case of an LCD driver 2 having a length of 6.0 mm from the leading end of the input testing terminals 6 to the trailing end of the output testing terminals 7. Therefore, LCD drivers 2 are to be arranged at two-pitch intervals of the sprocket holes 9, 10.
The output testing terminals 7 will be described next. Although the output testing terminals 7 are simply illustrated as being in a line in FIG. 10, the practical arrangement is such that every four terminals are arranged in four columns in the lengthwise direction of the substrate 1, as shown in FIG. 11. The multi-column arrangement of the output testing terminals 7 is determined according to the number of output terminals of the LCD driver chip 3, the minimum allowable size of the output testing terminal 7 determined by the probe pitch of a prober and the TCP width.
On the other hand, through the years, there has been examined a method for reducing the number of LCD drivers 2 to be used per LCD device by increasing the number of outputs of each LCD driver 2 in order to reduce the cost of the LCD module. According to this method, the multi-column arrangement of the output testing terminals 7 as described above is the indispensable condition, and the multi-column arrangement of four to six or more columns has been adopted depending on the number of outputs.
However, the aforementioned conventional TCP construction has the following problems. That is, according to the aforementioned TCP construction, the output testing terminals 7 are arranged in a multiplicity of columns. Therefore, the length from the foremost end of the input testing terminal 6 to the hindmost end of the output testing terminal 7 becomes long, and consequently the length of the substrate 1 becomes long. Then, the requirement that the arrangement pitch of the LCD driver chips 3 must be an integral multiple of the pitch of the sprocket holes 9, 10 standardized to 4.75 mm conspires to further increase the length of the substrate 1. Therefore, the substrate 1 is not effectively utilized. As a result, the cost per LCD driver 2 is disadvantageously increased.
Therefore, the object of the present invention is to provide a low cost semiconductor chip by effectively utilizing the substrate and reducing the testing time thereof. The present invention includes a semiconductor device package mounted with the semiconductor chip, a probe card for use in testing the semiconductor device package and a package testing method using the probe card.
In order to achieve the aforementioned object, the present invention provides a semiconductor chip having input terminals into which electric powers and signals are inputted, wherein
the input terminals are arranged so that electric powers of an identical electric potential or signals of an identical electric potential are supplied to the input terminals of same ordinal number when the terminals are viewed from both sides of the semiconductor chip.
According to the above construction, the input sequence of the signal to be inputted to the input terminal array of the semiconductor chip may be reversed. Furthermore, if the two semiconductor chips are arranged with their input terminals arranged opposite to each other, then the input terminals to which the electric power of an identical electric potential or the signal of an identical electric potential is inputted are arranged opposite to each other. Therefore, in the above case, no electric power short circuit occurs even when an identical electric power is supplied to the input terminals that are opposite to each other.
In one embodiment, adjoining two semiconductor chips are arranged so that a direction of either one of the chips is rotated at an angle of 180 degrees relative to the other.
According to the above construction, the adjoining two semiconductor chips are arranged in opposite directions. Therefore, the above construction enables the inputting of an identical electric power or signal to the input terminals that belong to the adjoining two semiconductor chips and are opposite to each other and enables the reduction of arrangement pitch by commonizing the input testing terminals of both the semiconductor chips.
In one embodiment, mutually opposite input terminals of the adjoining two semiconductor chips are connected together by way of an input lead, and
mutually opposite output terminals of the adjoining two semiconductor chips are connected together by way of an output lead.
According to the above construction, the distance between the input terminals and the distance between the output terminals of the adjoining two semiconductor chips can be reduced, and this allows the arrangement pitch per semiconductor chip to be reduced.
In one embodiment, the input lead is provided with an input testing terminal common to the adjoining two semiconductor chips, and
the output lead is provided with an output testing terminal common to the adjoining two semiconductor chips.
According to the above construction, the input testing terminal of either one of the adjoining two semiconductor chips and the output testing terminal of either one of the adjoining two semiconductor chips are eliminated, and this allows the distance between the input terminals and the distance between the output terminals to be reduced. The arrangement pitch per semiconductor chip is thus reduced.
The present invention also provides a semiconductor chip having input terminals into which an electric powers and signals are inputted, wherein
the input terminals are arranged so that electric powers of an identical electric potential or signals of an identical electric potential are supplied to part of input terminal pairs of same ordinal numbers when the terminals are viewed from both sides of the semiconductor chip.
According to the above construction, the signals to be inputted to the pair of input terminals to which the electric power of an identical electric potential or the signal of an identical electric potential is inputted may be reversed in the input terminals of the same ordinal numbers viewed from both ends of the semiconductor chip. Furthermore, if the two semiconductor chips are arranged with their input terminals arranged opposite to each other, then the input terminals to which the electric power of an identical electric potential or the signal of an identical electric potential is inputted are arranged opposite to each other. Therefore, no electric power short circuit occurs even when an identical electric power is supplied to the input terminals that are opposite to each other.
In one embodiment, adjoining two semiconductor chips are arranged so that a direction of either one of the chips is rotated at an angle of 180 degrees relative to the other.
According to the above construction, the adjoining two semiconductor chips are arranged in mutually opposite directions. Therefore, an identical electric power or signal can be inputted to the mutually opposite input terminals which belong to the adjoining two semiconductor chips and to which the electric power of an identical electric potential or the signal of an identical electric potential is to be inputted.
In one embodiment, the two semiconductor chips of which the input terminals are arranged opposite to each other function as a pair, and
mutually opposite output terminals of the adjoining two semiconductor chips are connected together by way of an output lead.
According to the above construction, the distance between the output terminals of the adjoining two semiconductor chips can be reduced, and this allows the arrangement pitch per semiconductor chip to be reduced.
In one embodiment, among the input terminals that are arranged opposite to each other in the two semiconductor chips that function as a pair, input terminals related to at least one pair to which the electric powers of an identical electric potential or the signals of an identical electric potential are supplied are connected together by way of a connection lead.
According to the above construction, the pair of input terminals that belong to the adjoining two semiconductor chips functioning as a pair and are connected by way of the connection lead can be commonized.
In one embodiment, the output lead is provided with an output testing terminal common to the adjoining two semiconductor chips,
an input testing terminal is connected to the input terminal of each semiconductor chip and the connection lead is provided between the mutually opposite input testing terminals.
According to the above construction, the output testing terminal of either one of the adjoining two semiconductor chips is eliminated, and this allows the distance between the output terminals to be reduced. The arrangement pitch per semiconductor chip is thus reduced.
In one embodiment, the package is a tape carrier package obtained by mounting the semiconductor chip on a tape-shaped substrate.
According to the above construction, the distance between the mutually opposite input terminals or the distance between the mutually opposite output terminals of the adjoining two semiconductor chips mounted on the tape-shaped substrate is reduced, by which the arrangement pitch of the semiconductor chip is reduced. Thus, the substrate is effectively utilized, achieving cost reduction.
In one embodiment, the package is a chip on film mounting package obtained by mounting the semiconductor chip on a rectangular substrate.
According to the above construction, the distance between the mutually opposite input terminals or the distance between the mutually opposite output terminals of the adjoining two semiconductor chips mounted on the rectangular substrate is reduced, by which the arrangement pitch of the semiconductor chip is reduced. Thus, the substrate is effectively utilized, achieving cost reduction.
A probe card of one embodiment comprises:
probes arranged so as to be able to be concurrently connected to the input testing terminal common to the adjoining two semiconductor chips and the output testing terminals of the adjoining two semiconductor chips, whereby
the adjoining two semiconductor chips can be tested by probing at one time.
According to the above construction, the input testing terminal to be probed by the probe card is the input testing terminal common to the adjoining two semiconductor chips. Then, the input terminals of the adjoining two semiconductor chips are arranged so that the electric powers of an identical electric potential or the signals of an identical electric potential are inputted to the input terminals of the same ordinal numbers when viewed from both ends of the respective semiconductor chips. Therefore, by supplying the signal and the electric power to the input testing terminal common to the adjoining two semiconductor chips and detecting the outputs of the respective output testing terminals of the semiconductor chips by means of the probe card, the adjoining two semiconductor chips are tested by proving at one time without a hitch.
A probe card of one embodiment comprises:
probes arranged so as to be able to be concurrently connected to the output testing terminal common to the adjoining two semiconductor chips and the input testing terminals of the adjoining two semiconductor chips, whereby
the adjoining two semiconductor chips can be tested by probing at one time.
According to the above construction, the output testing terminal to be probed by the probe card is the output testing terminal common to the adjoining two semiconductor chips. Therefore, by independently supplying the signals and the electric powers to the respective input testing terminals of the adjoining two semiconductor chips and successively detecting the output from the output testing terminal common to both the semiconductor chips, the adjoining two semiconductor chips are tested by probing at one time.
A probe card of one embodiment comprises:
probes arranged so as to be able to be concurrently connected to the input testing terminals of the two semiconductor chips that function as a pair and the output testing terminals of the two semiconductor chips, whereby
the two semiconductor chips that function as a pair can be tested by probing at one time.
According to the above construction, if the input terminals of the two semiconductor chips that function as a pair are arranged so that the electric powers of an identical electric potential or the signals of an identical electric potential are inputted to the input terminals of the same ordinal numbers when viewed from both ends of the respective semiconductor chips, then the test is executed as follows. That is, the identical signal and electric power are concurrently supplied to the input testing terminals of the two semiconductor chips, and the outputs of the output testing terminals of both the semiconductor chips are concurrently detected. The two semiconductor chips that function as a pair are thus tested by probing at one time.
Furthermore, if part of the input terminals of the two semiconductor chips that function as a pair are arranged so that the electric powers of an identical electric potential or the signals of an identical electric potential are inputted to the input terminals of the same ordinal numbers when viewed from both ends of the respective semiconductor chips, then the test is executed as follows. That is, the signal and the electric power are supplied to the input testing terminals of either one of the two semiconductor chips, and the output of the output testing terminal of the above semiconductor chip is detected. Next, the signal and the electric power are supplied to the input testing terminals of the other semiconductor chip, and the output of the output testing terminal of the above semiconductor chip is detected. The two semiconductor chips that function as a pair are thus tested by probing at one time.
A probe card of one embodiment comprises:
probes arranged so as to be able to be concurrently connected to the output testing terminal common to the adjoining two semiconductor chips and the input testing terminals of the adjoining two semiconductor chips, whereby
the adjoining two semiconductor chips can be tested by probing at one time.
According to the above construction, the output testing terminal to be probed by the probe card is the output testing terminal common to the adjoining two semiconductor chips. Therefore, by independently supplying the signals and the electric powers to the input testing terminals of the adjoining two semiconductor chips and successively detecting the outputs from the output testing terminal common to both the semiconductor chips, the adjoining two semiconductor chips are tested by proving at one time.
A package testing method of one embodiment comprises the step of:
applying mutually reversed signal input sequences or mutually reversed signal detection sequences to the adjoining two semiconductor chips with regard to at least one of the input testing terminals and the output terminals of the semiconductor chips when testing the adjoining two semiconductor chips by probing at one time.
According to the above construction, the sequence of signal input or the sequence of signal detection to or from the input testing terminals or the output terminals of one of the adjoining two semiconductor chips is reversed relative to the corresponding sequence of the input testing terminal or the output terminal of the other semiconductor chip. Therefore, the signal input or the signal detection of the adjoining two semiconductor chips are independently executed with the input testing terminals or the output terminals of the adjoining two semiconductor chips kept probed. That is, the test of the adjoining two semiconductor chips is independently executed by proving at one time.